Verilog

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The conversion of the schematic diagram into a VERILOG description is usefull for compiling the schematic diagram into layout using Microwind. The verilog description is a text with a predefined syntax. Basically, the text includes a description of the module (name, input, output), the internal wires, and the list of primitives. An example of veriolog file generated by DSCH is given below.

// DSCH 2.2a

// 24/06/01 18:38:13

// C:\Dsch 2.0\Manual uw2\Base.sch

module Base( A,B,INV,NAND,XOR,NOR);

input A,B;

output INV,NAND,XOR,NOR;

not1 not12(B,INV)

nand2 nand24(B,A,NAND)

xor2 xor27(A,B,XOR)

nor2 nor28(A,B,NOR)

endmodule

// Simulation parameters

// A CLK 10 10

// B CLK 20 20

COMMENTS: //

MODULE DECLARATION: "module", name, and list of I/Os.

MODULE CONTENTS: list of inputs, of outputs, of internal wires, and the declaration of primitives, always with the primitive keyword first, the name second, and the list of parameters. For example: NOT1 is the primitive for the inverter, "not12" is the cell name, "B" is the input and "INV" the output.

MODULE END: "endmodule".

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