Start/Stop Simulation (Simulate Menu)

The command "Start Simulation" launches the electrical net extraction and the logic simulation. The simulation speed may be controlled by the cursor "Fast-Slow". The simulation may be paused, run step by step and stopped. By default, the logic state of all interconnects is made visible. You may also see each pin state by a tic in front of "Show pin state".

The simulation parameters (Simulation Options) are: the simulation step (10ps by default), the gate delay, wire delay, supply voltage, and elementary gate current. This parameters are loaded from .TEC files at initialization or with the command File ® Select Foundry.

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